The present invention relates to a method of manufacturing a semiconductor integrated circuit device and a technique for a semiconductor integrated circuit device, and particularly to a technique for a semiconductor integrated circuit device having a memory in which an information storage capacity element is provided above a bit line.
A DRAM (Dynamic Random Access Memory) is known as a typical semiconductor memory among large capacity memories. The memory capacity of a DRAM tends to become larger and larger, and the occupied area of memory cells must be reduced accordingly from the viewpoint of improving the integration of memory cells of the DRAM. However, the storage capacity value of the capacitors must attain a certain amount regardless of generations, in consideration of operation margins of the DRAM and software errors. Therefore, the storage capacity value cannot be proportionally reduced in general.
Hence, to ensure a necessary storage capacity in a small allowed to be occupied area, a three-dimensional capacitor structure has been adopted, such as a so-called stack capacitor which is constructed by layering electrodes of two layers made of polysilicon or the like with a capacity insulating film inserted therebetween. An example thereof will be a so-called capacitor-over-bit line structure in which capacitors are arranged above bit lines.
A DRAM having this kind of structure is described in Japanese Patent Laid-open No. 6-268175. This reference discloses steps of manufacturing a DRAM as follows. At first, a gate electrode, is provided on the surface of a semiconductor substrate through a gate insulating film and a source and a drain are also formed on the surface of the semiconductor substrate. Thereafter, a first insulating film is accumulated on the semiconductor substrate. Contact holes for storage nodes and bit lines are simultaneously formed in the first insulating film. Subsequently, a polycrystalline silicon film is formed on the semiconductor substrate, and thereafter, this film is etched back to embed the polycrystalline silicon film in the two kinds of contact holes described above. Thereafter, another new polycrystalline silicon film for forming bit lines and an insulating film above the polycrystal silicon film are deposited, and further, the polycrystalline silicon film is etched and removed within regions other than the bit lines, with a photoresist used as a mask. Through these steps, the surface of the polycrystalline silicon film within the contact holes for storage nodes is lower than the surface of the first insulating film. Thereafter, a side wall film made of an insulating film is formed on the side surface on which there is no polycrystalline silicon film of the contact holes for storage nodes and on the side surface of the polycrystal silicon film which form bit lines. Thereafter, storage nodes are formed.
Further, Japanese Patent Laid-open No. 6-338597 discloses a technique of forming bit lines of a DRAM by means of embedded wires. That is, a bit line is formed by forming a groove in an insulating film and by embedding a conductive film in the groove. This bit line is arranged in a flat and linear form. In addition, the active region (source-drain region) of the memory cell selection MOSFET is formed in a flat T-shaped form. The bit line is arranged to be layered flat on a convex portion in the center of the active region, and is connected to the active region at the layering region through a contact hole formed in the insulating film.
However, the present inventors have found that the DRAM having the above-mentioned capacitor-over-bit line structure encounters the following problems.
In the technique described in the Japanese Patent Laid-open 6-268175, bit lines and conductive members in the contact holes for bit lines are formed in different steps, so that contact resistance is caused between the bit lines and the members. Therefore, due to voltage drops of bit lines caused by contact resistance, the DRAM is not suitable for operation with a low voltage or operation at a high speed. In the case described above, the bit lines and the conductive members in the contact holes for the bit lines are made of same material of polycrystalline silicon films. Also in this case, since the steps for forming these components are not continuous, there is a problem that a silicon oxide film tends to be formed at the boundary therebetween and causes contact resistance. (Normally, a silicon oxide film is very thin and allows a tunneling current to flow. In addition, a silicon oxide film is partially formed due to unevenness of concentration in the polycrystalline silicon film or due to influences from grains, thereby allowing a current to flow.)
Also, in this technique, a pattern of bit lines is formed on an insulating film. Since a side wall insulating film is formed on the side surfaces of the bit line, it is relating easy to ensure flatness. However, convex and concave portions reflecting the st eps of the pattern of the bit lines are formed on the upper surface of the insulating film covering the bit lines. As a result, when the storage node electrodes are formed by patterning on the insulating film, non-etched portions can be left on the side wall at the st eps on the upper surface of the insulating film, and short-circuiting error tends to occur due to the non-etched portions.
In addition, the technique described in the Japanese Patent Laid-open No. 6-338597 discloses a structure in which bit lines are formed of embedded wires. This is a technique relating to a DRAM which is different from the structure of the present invention.